Embodiments of the invention relate to integrated circuits, and in particular, initializing and testing integrated circuits.
An integrated circuit comprises a set of electronic circuits disposed on a semiconductor wafer or substrate. The set of electronic circuits may include multiple processing elements. There are different types of processing elements, such as microprocessors, microcontrollers, digital signal processors, graphics processors, reconfigurable processors, fixed function units, hardware accelerators, neurosynaptic neural core circuits, etc. The processing elements may be arranged in a one-dimensional grid arrangement, a two-dimensional grid arrangement, a three-dimensional grid arrangement, or in a ring or torus topology. The processing elements may be interconnected, thereby enabling packet communication between the processing elements.
Manufacturing testing of a semiconductor integrated circuit is an essential part of the production of the processing elements. Typically, manufacturing testing is carried out using a scanning methodology that scans in test data into an integrated circuit with a scan chain. A scan chain may comprise long shift registers. A test is then run by driving the integrated circuit using the scanned in test data, and collecting test results for the integrated circuit. The test results are scanned out of the scan chain.
The bigger/larger the size of an integrated circuit, the longer its scan chain. As such, it takes a proportionally longer time to scan in test data and scan out test results for a bigger/larger-sized integrated circuit, thereby increasing the time for testing the integrated circuit and increasing the cost of production. A number of compression schemes and built-in-test circuits are available to mitigate this problem. However, a built-in-test circuit consumes area and power, and increases the complexity of the integrated circuit.
For example, in a processing system with multiple units on a chip (e.g., many-core processors, neuromorphic processors, GPU, and FPGA chips), implementing a built-in-test circuit for each unit becomes cost prohibitive. Further, implementing a centralized built-in-test circuit for the processing system may not easily resolve the problems of increased time for testing and increased complexity of the integrated circuit.
Further, if a scan chain is also used to initialize an integrated circuit, a longer scan chain may lead to slow bring-up time of a digital system implemented using the integrated circuit. Fast scan chaining system are needed for speedy initialization. For example, in an integrated circuit that may not have a high speed clock (e.g., a neuromorphic circuit), fast initialization of the integrated circuit using a slow clock is essential.